Hardware Architecture for Modified Sequential LDPC Decoder

Iterative decoding of Low Density Parity Check (LDPC) codes using the Parity Likelihood Ratio (PLR) algorithm have been proved to be more efficient compared to conventional Sum Product Algorithm (SPA). However, the nature of PLR algorithm tends to put numerious pieces of data to this decoder and perform computation intensive operations, which is a major challenge for building a practical real-time LDPC decoder. In this paper, it makes use of extrinsic information clipping and calculation step merging techniques to simplify the decoding algorithm. These approaches reduce the number of quantization levels while still remaining the algorithmic performance promised by random codes. Moreover, a modified sequential architecture is proposed for LDPC decoding that decreases the decoding latency and reduces the memory storage compared to existing direct sequential design. Simulation results show that the proposed architecture results in time and memory savings of up to 92.26% and 59.56% respectively over conventional direct sequential implementation. Key-Words: LDPC codes, sequential architecture, VLSI implementation, PLR algorithm